PARTNERSHIPS
Patent Notice
Aeonic Generate™ Patents
| Patent Number | Patent Title | Country of Issue |
|---|---|---|
| US9641183B2 | DUAL-LOOP PROGRAMMABLE AND DIVIDERLESS CLOCK GENERATOR FOR ULTRA LOW POWER APPLICATIONS | United States |
| US9515668B2 | AUTOMATICALLY PLACE-AND-ROUTED ADPLL WITH PWM-BASED DCO RESOLUTION ENHANCEMENT | United States |
| US10158365B2 | DIGITAL, RECONFIGURABLE FREQUENCY AND DELAY GENERATOR WITH PHASE MEASUREMENT | United States |
| US10587275B2 | LOCKED LOOP CIRCUIT WITH CONFIGURABLE SECOND ERROR INPUT | United States |
| US9698798B1 | DIGITAL CONTROLLER FOR A PHASE-LOCKED LOOP | United States |
| US9680480B1 | FRACTIONAL AND RECONFIGURABLE DIGITAL PHASE-LOCKED LOOP | United States |
| US9705516B1 | RECONFIGURABLE PHASE-LOCKED LOOP WITH OPTIONAL LC OSCILLATOR CAPABILITY | United States |
| US9762249B1 | RECONFIGURABLE PHASE-LOCKED LOOP | United States |
| US10594323B2 | LOCKED LOOP CIRCUIT WITH DIGITALLY-CONTROLLED OSCILLATOR (DCO) GAIN NORMALIZATION | United States |
| US10594323B2 | LOCKED LOOP CIRCUIT WITH DIGITALLY-CONTROLLED OSCILLATOR (DCO) GAIN NORMALIZATION | United States |
| US11070215B2 | LOCKED LOOP CIRCUIT WITH DIGITALLY-CONTROLLED OSCILLATOR (DCO) GAIN NORMALIZATION | United States |
| US11070216B2 | LOCKED LOOP CIRCUIT WITH DIGITALLY-CONTROLLED OSCILLATOR (DCO) GAIN NORMALIZATION | United States |
| US11239849B2 | LOCKED LOOP CIRCUIT AND METHOD WITH MULTI PHASE SYNCHRONIZATION | United States |
| US11831318B1 | FREQUENCY MULTIPLIER SYSTEM WITH MULTI-TRANSITION CONTROLLER | United States |
| US11493950B2 | FREQUENCY COUNTER CIRCUIT FOR DETECTING TIMING VIOLATIONS | United States |
Aeonic Connect™ Patents
| Patent Number | Patent Title | Country of Issue |
|---|---|---|
| US10713409B2 | INTEGRATED CIRCUIT DESIGN SYSTEM WITH AUTOMATIC TIMING MARGIN REDUCTION | United States |
| US10972106B1 | PHASE AND DELAY COMPENSATION CIRCUIT AND METHOD | United States |
| US11165432B1 | GLITCH-FREE DIGITAL CONTROLLED DELAY LINE APPARATUS AND METHOD | United States |
| US11374578B2 | ZERO-OFFSET PHASE DETECTOR APPARATUS AND METHOD | United States |
| US20220200604A1 | DIGITAL SYSTEM SYNCHRONIZATION | United States |
Company-Wide Patents
| Patent Number | Patent Title | Country of Issue |
|---|---|---|
| US10614182B2 | TIMING ANALYSIS FOR ELECTRONIC DESIGN AUTOMATION OF PARALLEL MULTI-STATE DRIVER CIRCUITS | United States |
| US10031992B2 | CONCURRENTLY OPTIMIZED SYSTEM-ON-CHIP IMPLEMENTATION WITH AUTOMATIC SYNTHESIS AND INTEGRATION | United States |
| US10740526B2 | INTEGRATED CIRCUIT DESIGN SYSTEM WITH AUTOMATIC TIMING MARGIN REDUCTION | United States |
| US11017138B2 | TIMING ANALYSIS FOR ELECTRONIC DESIGN AUTOMATION OF PARALLEL MULTI-STATE DRIVER CIRCUITS | United States |
| US10972119B1 | REGULATED CHARGE SHARING ANALOG-TO-DIGITAL CONVERTER (ADC) APPARATUS AND METHOD | United States |
| US11128308B2 | REGULATED CHARGE SHARING APPARATUS AND METHODS | United States |
| US10972115B1 | METHODS AND APPARATUS FOR CALIBRATING A REGULATED CHARGE SHARING ANALOG-TO-DIGITAL CONVERTER | United States |
| US11496139B2 | FREQUENCY MEASUREMENT CIRCUIT WITH ADAPTIVE ACCURACY | United States |
