Knowledge Center

Academic and Industry Papers

PreviewTitleResource TypeSummary
Synchronous Die-to-Die Signaling Using Aeonic ConnectAcademic Paper,
6 pages
Presented at CICC 2023, Movellus explores a single-cycle die-to-die solution that is 3-5x lower power than existing standards

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Movellus Attacks Voltage DroopIndustry Paper,
5 pages
Movellus debuts its Aeonic™ Integrated Droop Response System that takes critical steps in mitigating an issue that is affecting an increasing number of chips. Authored by Bryon Moyer at Techinsights.

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Movellus Aeonic: An Intelligent Clock NetworkWhite Paper,
8 pages
Movellus is increasing silicon clock performance, power, and reliability through its Aeonic technology, which uses optimized IP to mitigate on-chip variation, skew, and voltage droop for high-performance and low-power devices. Authored by The Linley Group

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Whitepapers

PreviewTitleResource TypeSummary
Movellus Aeonic: An Intelligent Clock NetworkWhite Paper,
8 pages
Movellus is increasing silicon clock performance, power, and reliability through its Aeonic technology, which uses optimized IP to mitigate on-chip variation, skew, and voltage droop for high-performance and low-power devices. Authored by The Linley Group

Click here to download the white paper!

Use Cases

PreviewTitleResource TypeSummary
Distributed Clocking for Sea of Processor SoCsUse Case Summary,
2 pages
Learn more about how Aeonic Generate CGMs and distributed clocking enables fine-grain performance tuning for sea of processor architectures.

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Remote Droop Detection and Response Use Case
Use Case Summary,
2 pages
Learn more about how the Aeonic™ Integrated Droop Response System enables remote droop detection and response for complex SoCs.

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Localized Droop Detection and Response Use Case
Use Case Summary,
2 pages
Learn more about how the Aeonic™ Integrated Droop Response System enables localized droop detection and response for sea of processor architectures.

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Droop Detection and Response for Heterogeneous SoCsUse Case Summary,
2 pages
Learn more about how the Aeonic™ Integrated Droop Response System enables localized droop detection and response for heterogeneous SoCs.

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Product Briefs and Data Sheets

PreviewTitleResource TypeSummary
Aeonic Power™ HC Solution BriefSolution Brief,
3 pages
  • Enables per-core DVFS
  • Programmable through standardized interfaces
  • Localized IR drop mitigation
  • Virtual power islands
  • Process Portable

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Aeonic Power™ LN Solution BriefSolution Brief,
2 pages
  • Eliminates inductive filters
  • Isolates die-to-die (D2D) rails
  • Simplifies PDN
  • Telemetry
  • Virtual power islands
  • Process Portable

Click here to learn more about Aeonic Power™ LN!
Aeonic Generate™ AWM3 Solution BriefSolution Brief,
2 pages
  • <2 cycle droop response
  • Enables distributed and localized clocking
  • Operates on core voltage (VDD), no VDDA required
  • Telemetry
  • Post-Silicon Programmability
  • Process Portable

Click here to learn more about Aeonic Generate™ AWM3!
Aeonic Generate™ CGM Solution BriefSolution Brief.
2 pages
  • Enables distributed and localized clocking
  • Operates on core voltage (VDD), no VDDA required
  • Telemetry
  • Post-Silicon Programmability
  • Process Portable

Click here to learn more about Aeonic Generate™ CGM!
Aeonic Insight™ Droop Detector Solution BriefSolution Brief,
2 pages
  • In-test and in-field PDN monitoring
  • Multi-threshold droop detection
  • Telemetry
  • Automated Calibration
  • Industry leading response time
  • Process Portable

Click here to learn more about Aeonic Insight™ Droop Detector!
Aeonic™ Integrated Droop Response Solution BriefSolution Brief,
3 pages
  • Reduce chip-level Vmin
  • Single-cycle droop detection and response
  • Multi-threshold droop detection
  • Post-silicon programmability
  • Droop-specific telemetry for silicon analytics engines


Click here to learn more about Aeonic™ Integrated Droop Response System!