Aeonic™ Integrated Droop
Response System
The Aeonic Integrated Droop Response System revolutionizes the way we respond to droop in complex integrated circuits. This innovative solution is designed to simultaneously mitigate voltage droop and enable fine-grained DVFS capability in an integrated turnkey solution, resulting in significant power savings for SoCs.
It also includes extensive observability features that provides valuable insight for modern silicon health and lifecycle management systems. With its fast adaptation time, multi-threshold droop detection, remote/local droop detection support, APB & JTAG interfaces, this system helps architects manage droop and DVFS while generating actionable insights for silicon health and analytics platforms.
Tightly Coupled
The Aeonic™ Integrated Droop Response system tightly couples droop mitigation and detection for the fastest adaptation time that is commercially available. By detecting and responding to droop in less than three high-speed clock cycles, design teams can reduce voltage margin and reduce system power by more than 10%.
Observable
The system generates droop-specific outbound data for silicon health and analytics management. It also allows for post-silicon programmability to keep pace with silicon aging.
Process Portable
Featuring a standard cell design, the integrated droop response system effectively scales with process technology. Design teams can remain confident that features will reliably move from node-to-node.
Product Line Highlights
Process Portable
Fully synthesizable for feature-rich system-level solutions..
Silicon Lifecycle Analytics Support
Functional IP that generates actionable insight.
Programmable
Tunable features driven by silicon analytics.
Patent Notice may be found at: www.movellus.com/patent-notice.
