Presented at DAC 2024 –

SoCs designed for compute-intensive workloads, such as AI training and inferencing, continue to grow and power budgets are increasing geometrically. Power consumption is comprised of dynamic and static power elements. The latter is generally fixed and determined by process technology and design techniques, while the former depends on workloads and frequency. This variability of workloads can drive rapid changes in current draw, which causes voltage droop, a rapid drop in power rails that can lead to timing glitches and system failures. For example, sudden changes in models or weights can drive these sudden shifts in workloads causing voltage droops.

Silicon design teams have attempted to address droop in various ways, but all methods have significant downsides. The typical options employed are increasing voltage margins, reducing operating frequencies, scheduling workloads through software, or using active droop mitigation methods that may be fully custom or tailored to their needs. Each of these solutions has advantages and drawbacks regarding power, performance, and implementation effort.

This discussion will explore the root causes of droop, its impact on power, and the increasing challenges in advanced nodes. It will also delve into modern droop mitigation techniques, highlighting the advantages of a tightly-coupled, synthesizable solution.